1. Field of the Invention
The present disclosure generally relates to the field of integrated circuits, and, more particularly, to heat dissipation and thermal management of semiconductor devices.
2. Description of the Related Art
In modern integrated circuits, a very high number of individual circuit elements, such as field effect transistors in the form of CMOS, NMOS, PMOS elements, resistors, capacitors and the like, are formed on a single chip area. Typically, feature sizes of these circuit elements are continuously decreased with the introduction of every new circuit generation to provide currently available integrated circuits formed by volume production techniques with critical dimensions of 50 nm or less and having an improved degree of performance in terms of speed and/or power consumption. A reduction in size of transistors is an important aspect in steadily improving device performance of complex integrated circuits, such as CPUs. The reduction in size is commonly associated with an increased switching speed, thereby enhancing signal processing performance at transistor level.
In addition to the large number of transistor elements, a plurality of passive circuit elements, such as capacitors, resistors, interconnect structures and the like, are typically formed in integrated circuits as required by the basic circuit layout. Due to the decreased dimensions of the active circuit elements, not only the performance of the individual transistor elements may be increased, but also their packing density may be improved, thereby providing the potential for incorporating increased functionality into a given chip area. For this reason, highly complex circuits have been developed, which may include different types of circuits, such as analog circuits, digital circuits and the like, thereby providing entire systems on a single chip (SoC).
The increased packing density of integrated circuits resulting from the reduced device dimensions may also be accompanied by reduced switching speeds of the individual transistors in complex logic circuitry, thereby contributing to increased power consumption in MOS circuits, since the reduced switching speeds allow the operation of the transistors at higher switching frequencies, which in turn increases the power consumption of the entire device. Therefore, in sophisticated applications using densely packed integrated circuits, the heat generation may reach extremely high values due to the dynamic losses caused by the high operating frequency in combination with a significant static power consumption of highly scaled transistor devices owing to increased leakage currents that may stem from extremely thin gate dielectrics, short channel effects and the like. Therefore, great efforts are being made in order to reduce overall power consumption by restricting the usage of high performance transistors, which usually cause higher heat generation, to performance critical signal paths in the circuit design, while using less critical devices in other circuit areas. Moreover, appropriate mechanisms may be implemented to operate certain circuit portions “on demand” and control local or global operating conditions depending on the thermal situation in the semiconductor die.
The heat generated during the operation of the internal circuit elements is typically dissipated via the substrate material or the complex metallization system including highly conductive metals and sophisticated dielectric materials, depending on the overall configuration of the semiconductor device, the package accommodating the semiconductor device and the contact regime for connecting the metallization system to the wiring system of the package. Finally, the internally generated heat has to be transferred to the package and to an external cooling system connected to the package. Thus, a wide variety of cooling systems are typically used, with complex passive architectures, such as specifically designed heat sinks and heat pipes, and also expensive active cooling devices, for instance in the form of fans, water cooling systems, Peltier elements and the like. With the quest for high performance of complex semiconductor devices, the corresponding power consumption of semiconductor devices, such as microprocessors, have reached the 100 Watt range, while the shrinking technology ground rules have resulted in increased thermal density of these semiconductor devices, as more transistors are packed into a smaller die region. External heat management systems, e.g., systems which may be operated on the basis of the internal thermal state of the semiconductor device, may not permit a reliable estimation of the die internal temperature distribution due to the delayed thermal response of the package of the semiconductor device and the possibly insufficient spatial temperature resolution of device internal temperature monitoring systems. Accordingly, external cooling systems may have to be designed to take into consideration these restrictions and to provide sufficient operational margins with respect to heat control unless a certain risk of overheating, and thus possibly damaging specific critical circuit portions, may be caused.
FIG. 1a schematically illustrates a representation of the power density of advanced integrated devices for various technology standards, while a corresponding total thermal power window, that is, reliable margins for operating the device, is also depicted. For example, curve A in FIG. 1a illustrates an over-proportional increase of the power density, that is, the heat created per unit area of a semiconductor die, wherein the slope of the increase may become significantly steeper for a technology standard of 65 nm. On the other hand, curve B represents the corresponding progression of the allowable total thermal power, which may have to be respected in operating corresponding devices, which may substantially be determined by the overall heat dissipation capabilities of the semiconductor devices under consideration. Consequently, since a substantially linear increase of the total thermal power margins may be observed with the scaling of the device dimensions, while, on the other hand, the power density may over-proportionally increase, a corresponding adaptation of heat dissipation systems may be required, thereby resulting in extremely complex external cooling systems. That is, conventional available solutions rely on passive cooling devices, such as a metallic heat sink, to remove heat from the surface of the device, i.e., the package, and to transfer the heat to the ambient atmosphere by convection. Frequently, an active device, such as an exhaust fan, is added to the passive thermal cooling system to increase the rate of thermal energy removal in applications, where passive cooling is not sufficient to dissipate sufficient thermal energy so as to avoid physical damage to the system during full power operation.
FIG. 1b schematically illustrates a semiconductor device in combination with a conventional cooling system. As illustrated, an electronic system 150 comprises a semiconductor device 100, which may represent any complex integrated circuit, such as a microprocessor, a mixed signal system including power devices, small signal circuit portions, complex analog circuitry and the like, which may include transistor elements with extremely scaled critical dimensions, for instance in the range of 50 nm and less. The semiconductor device 100 is typically attached to a package 160, which may comprise a package lid 162 and a package substrate, which may comprise an appropriate wiring system so as to connect to the metallization system of the semiconductor device 100. For example, corresponding bond wires (not shown) may connect to complementary bond pads formed on a final metallization layer of the semiconductor device 100, while, in other cases, a direct contact of the package and the semiconductor device 100 may be established on the basis of an appropriate bump structure, as will be described later on in more detail. Moreover, in sophisticated applications, an appropriate material 163, also referred to as thermal interface material, is frequently provided to enhance the thermal conductivity for transferring heat from the semiconductor device 100 to the package lid 162 via the highly conductive material 163. Furthermore, the package lid 162 is in turn in contact with a cooling system 170, which comprises a passive component 171, for instance in the form of a metal cover having a high thermal conductivity and an increased surface area for enhancing heat transfer to the ambient. Furthermore, in more sophisticated applications, one or more active cooling devices 172, such as a fan and the like, may be provided to further enhance the heat dissipation from the passive component 171 to the ambient atmosphere. It should be appreciated that other exotic and expensive solutions for the cooling system 170 may frequently be used, in which, additionally or alternatively, liquid cooling designs and refrigeration may be implemented to increase the rate of thermal energy removal, thereby allowing semiconductor devices of ever-increased power consumption to function without sustaining thermally-induced damage. However, as the complexity of the cooling system 170 may increase, the corresponding costs increase and a higher rate of failure may be observed. Furthermore, increasing the thermal capacity of the external cooling system 170 in view of enabling even further increased power densities in the semiconductor device 100 may typically require an increase in size, for instance for the passive component 171, and/or capability of the active components, for instance of the component 172, may have to be increased, for instance by increasing fan speed for increasing the air volume and the like. For large scale systems, such as server farms, these active/passive cooling systems increase cost and complexity due to the dense installations required. Typically, the ability for decreasing system space requirements is reduced, as this could compromise the ability to implement larger cooling solutions necessary for safe operation. Furthermore, using sophisticated active devices in the cooling system may significantly increase the probability of creating damage in the equipment due to a failure of these complex active components, thereby contributing to increased system down time, while also increasing power consumption and thus overall cost of ownership compared to an all passive system.
FIG. 1c schematically illustrates the semiconductor device 100 in a cross-sectional view, wherein the overall heat dissipation capability may even further be restricted due to the internal configuration of the device 100. As illustrated, the semiconductor device 100 may be configured so as to be connected to a package by directly attaching a metallization system 120, which may comprise an appropriately configured bump structure, to a corresponding wiring system of the package. Thus, the heat may be dissipated via a substrate 101, which may finally be connected to an external interface, such as the thermal interface material 163. Consequently, in conventional strategies for increasing the dissipation capability of an electronic system, such as the system 150 as shown in FIG. 1b, the thermal interface material 163 may be modified to improve the overall thermal efficiency of the cooling system 170 (FIG. 1b). As discussed above, in other cases, the passive and active components of the corresponding cooling system may be increased or improved with respect to the heat dissipation capability. In the device 100 as shown in FIG. 1c, a significant improvement of the heat dissipation capability of the metal 163 in contact with the substrate 101 may result in a very limited overall improvement of the thermal condition in the device 100, since, in sophisticated device architectures, frequently, a buried insulating layer 102 may be provided, at least in performance driven device areas, in order to electrically insulate the substrate 101 from an active silicon layer 103. The silicon layer 103 may represent a part of a device level 110, in which circuit elements 111, such as transistors, resistors and the like, are formed. Furthermore, these circuit elements 111 are connected to a metallization system 120 which may have a highly complex configuration, as previously explained. Thus, upon operating the semiconductor device 100, heat generated by the circuit elements 111, for instance by fast switching transistor elements in complex logic circuit portions, is transferred to the substrate 101 and is finally dissipated via the interface 163. Due to the direct contact of the metallization system 120 with a corresponding wiring system of the package, a certain amount of heat may also be dissipated via the metallization system 120, depending on the heat dissipation capability of the corresponding package material in combination with the package internal wiring system. However, typically, the provision of sophisticated heat dissipation components may not be possible, since, typically, the package may connect to a printed wiring board and the like, thereby significantly reducing the possibility of providing additional heat dissipation areas, unless a significant increase of the overall length of the corresponding conductors is used, which may be disadvantageous with respect to the overall electrical performance. On the other hand, the heat transfer to the interface 163 via the substrate 101 may be significantly reduced due to the presence of the buried insulating layer 102, which may have an inferior thermal conductivity compared to the substrate 101 and the semiconductor layer 103. Consequently, the heat dissipation capabilities for highly sophisticated semiconductor devices, which may frequently comprise a silicon-on-insulator (SOI) architecture, may significantly restrict the packing density in the device level due to the restrictions with respect to overall power density, while, in other cases, sophisticated re-designs may have to be used in order to maintain the total thermal die power within the specifications for full power operation.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.